This inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having capacitors in a peripheral circuit region.
As the integration density of semiconductor memory devices, for example, a dynamic random access memory (DRAM) device, increases, the demand for increasing the operating speed of the semiconductor memory device as well as the demand for increasing the storage capacity of the semiconductor memory device have also increased. Accordingly, a capacitor having various functions is required in a peripheral circuit of the semiconductor memory device.
In general, when the integration density of a semiconductor memory device is increased, the number of operating circuits is increased in proportion to the increase in the integration density of the semiconductor memory device. As a result, severe fluctuation noise can instantly be caused to a power source voltage VDD and a ground voltage VSS when a reading operation or a writing operation starts. In order to address this problem, a semiconductor memory device conventionally includes a power decoupling capacitor for filtering noise present between operational power sources, such as the power source voltage VDD and the ground voltage VSS. An internal voltage boosting circuit is a pumping circuit for forming a power source, for example, a bulk bias VBB and a boost voltage VPP that are not inputted from the outside, and includes at least one pumping capacitor to store charges in one stage and to transmit the charges in a subsequent stage.
In this peripheral circuit (e.g., the power decoupling capacitor and the pumping capacitor), however, there is often a problem where the effective capacitance is substantially reduced under high frequency conditions due to a high resistance.